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CY7C64613
EZ-USB FXTM USB Microcontroller
Cypress Semiconductor Corporation Document #: 38-08005 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 22, 2003
CY7C64613
TABLE OF CONTENTS 1.0 FEATURES ...................................................................................................................................... 4 1.1 EZ-USB FX Features .................................................................................................................. 4 1.2 Example Applications .................................................................................................................. 5 1.3 Other Resources ......................................................................................................................... 6 2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 6 2.1 Microprocessor ........................................................................................................................... 6 2.2 USB SIE ...................................................................................................................................... 6 2.3 GPIF (General Programmable InterFace) ................................................................................... 6 2.4 Slave FIFOs ................................................................................................................................ 6 2.5 DMA ............................................................................................................................................ 7 2.6 Flexible Configuration ................................................................................................................. 7 2.7 Endpoints .................................................................................................................................... 9 2.8 Default USB Machine ................................................................................................................ 10 2.9 IBN (In-Bulk-NAK) Interrupts ..................................................................................................... 10 3.0 PINS ............................................................................................................................................... 11 3.1 Pin Diagrams ............................................................................................................................ 11 3.2 General Notes About the Pin Description Table ....................................................................... 14 3.3 CY7C64613 Pin Descriptions ................................................................................................... 14 4.0 REGISTER SUMMARY .................................................................................................................. 23 5.0 INPUT/OUTPUT PIN SPECIAL CONSIDERATION ...................................................................... 29 6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 29 7.0 OPERATING CONDITIONS ........................................................................................................... 29 8.0 DC CHARACTERISTICS ............................................................................................................... 29 9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 30 9.1 USB Transceiver ....................................................................................................................... 30 9.2 Program Memory Read ............................................................................................................. 30 9.3 Data Memory Read ................................................................................................................... 31 9.4 Data Memory Write ................................................................................................................... 32 9.5 DMA Read ................................................................................................................................ 33 9.6 DMA Write ................................................................................................................................. 34 9.7 Slave FIFOs--Output Enables .................................................................................................. 35 9.8 Slave FIFOs--Synchronous Read ............................................................................................ 35 9.9 Slave FIFOs--Synchronous Write ............................................................................................ 36 9.10 Slave FIFOs--Asynchronous Read ........................................................................................ 36 9.11 Slave FIFOs--Asynchronous Write ........................................................................................ 37 9.12 GPIF - Clocked with Fixed 48-MHz Internal Clock ................................................................. 37 9.13 GPIF Signals Externally Clocked - XCLK ............................................................................... 38 10.0 ORDERING INFORMATION ........................................................................................................ 38 11.0 PACKAGE DIAGRAMS ............................................................................................................... 38 11.1 52 PQFP ................................................................................................................................. 39 11.2 80 PQFP ................................................................................................................................. 40 11.3 128 PQFP ............................................................................................................................... 41 11.3 128-Lead Plastic Quad Flatpack ............................................................................................. 41
Document #: 38-08005 Rev. *B
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CY7C64613
LIST OF FIGURES Figure 1-1. CY7C64613 Block Diagram .................................................................................................. 4 Figure 2-1. General Scheme of Multiplexed Pins for the 128-pin CY7C64613 ....................................... 8 Figure 3-1. CY7C64613 52-pin PQFP Assignment ............................................................................... 11 Figure 3-2. CY7C64613 80 Pin PQFP Assignment ............................................................................... 12 Figure 3-3. CY7C64613 128 Pin PQFP Assignment ............................................................................. 13
Document #: 38-08005 Rev. *B
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CY7C64613
1.0 Features
The CY7C64613 (EZ-USB FX) is Cypress Semiconductor's second-generation full-speed USB family. FX products offer higher performance and a higher level of integration than first-generation EZ-USB products. FX builds on the EZ-USB feature set, including an intelligent USB core, enhanced 8051, 8-Kbyte RAM, and high-performance I/O while maintaining upward code compatibility. The CY7C64613 enhances the EZ-USB family by providing faster operation and more ways to transfer data into and out of the chip at very high speed.
12 MHz A DDR(16) Data (8)
G PIF
X4 PLL
8051 Core 48 / 24 MHz, 4-c lock ins truc . cy cle
UA RT0
UA RT1
3 Timers
USB Trans c eiv er
Data Bus (8)
Up to 5 I/O Ports (Ports A -E)
USB
Enhanc ed USB Serial Interf ac e Engine (SIE)
8 KB RA M
4 FIFOs Eac h 64 by tes
8/16 bits
2 KB FIFO (ISO) DMA Engine I 2 C Compatible Controller
C Y7C 64613
Figure 1-1. CY7C64613 Block Diagram
1.1
EZ-USB FX Features
* Single-chip integrated USB Transceiver, Serial Interface Engine (SIE), and enhanced 8051 microprocessor * Certified compliant with USB Specifications 1.1 and 2.0 (full-speed device) * Software operation: 8051 runs code from internal RAM or external RAM. Code can be: -- Downloaded via USB -- Loaded from EEPROM -- Executed in-place from external memory (e.g., Flash) * Abundant endpoints and buffers -- 14 Bulk/Interrupt endpoints, each with a maximum packet size of 64 bytes (per USB specification) -- 16 Isochronous endpoints, with 2 KB of buffer space (1 KB, double buffered) which may be divided among the 16 isochronous endpoints -- One control endpoint (bidirectional) * Integrated, industry standard 8051 with enhanced features: -- Four clocks per instruction cycle -- 48-MHz or 24-MHz 8051, selectable by EEPROM configuration bit -- Two UARTS (115 K baud) -- Three counter/timers -- Expanded interrupt system -- Two data pointers * 3.3V operation * Smart SIE Document #: 38-08005 Rev. *B Page 4 of 42
CY7C64613
-- Handles much of the low-level USB protocol in logic, simplifying 8051 code * General Programmable InterFace (GPIF) -- Allows direct connection to most parallel interfaces: 8- and 16-bit wide -- Eliminates external glue logic in most applications -- Programmable Waveform Instructions and Configuration Registers to define waveforms -- Six Ready (RDY) inputs and six Control (CTL) outputs * Vectored interrupt system expanded for USB, FIFO flags and DMA interrupts * Separate buffers for SETUP and DATA portions of a CONTROL transfer * Integrated I2C-compatible controller -- 400-KHz or 100-KHz operation * Enhanced I/O -- I/O port registers mapped to 8051 SFRs (Special Function Registers) for high-speed bit operations -- Port bits can be controlled using 8051 bit addressing instructions -- Up to five 8-bit I/O ports * Four integrated 8-bit-wide FIFOs -- Each 64 bytes deep -- Automatic conversion to and from 16-bit buses -- Easy, glueless interface to ASIC, DSP ICs and external logic -- Brings glue FIFOs inside for lower system cost -- Internal or external clock -- Synchronous (using strobes and a clock) or asynchronous (using strobes only) * DMA controller -- Moves data between slave FIFOs, memory, and ports -- Very fast transfers--one clock (20.8 ns = 48 MHz) per byte for internal transfers -- Can use external RAM as additional FIFO (accessed via Address and Data buses) * Special Autovectors for DMA and FIFO interrupts * Glueless external memory expansion -- Up to 16-bit address bus and 8-bit data bus -- Strobes RD#, WR#, OE#, CS#, and PSEN# -- Buses not multiplexed (as in standard 8051), saving one clock per external memory cycle * Three package options-128-pin PQFP, 80-pin PQFP, and 52-pin PQFP
1.2
Example Applications
* DSL modems * ATAPI interface * Memory card readers * Legacy conversion devices * Cameras * Scanners * Home PNA * Wireless LAN * MP3 players * Networking
Document #: 38-08005 Rev. *B
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CY7C64613
1.3 Other Resources
Other sources of EZ-USB FX information include: * EZ-USB FX Technical Reference Manual (TRM), Version 1.2 or higher * CY3671 EZ-USB FX Development Kit * The web site www.cypress.com, which includes information about many Reference Designs, such as USB Mass Storage Device, ADSL modem, MPEG.2 players, etc.
2.0
2.1
Functional Overview
Microprocessor
The CY7C64613 uses a 12-MHz crystal for low EMI. An internal oscillator and PLL develops an internal 48-MHz clock for use by the USB Serial Interface Engine and the 8051 microprocessor. The 8051 can run at either 24 MHz or 48 MHz, controlled by a bit in the EEPROM attached to the I2C-compatible bus. The default rate (with no EEPROM connected) is 24 MHz. The internal microprocessor is an enhanced version of the industry-standard 8051. Enhancements include four clocks per instruction cycle operation, a second data pointer, and an enhanced interrupt system. The 8051 includes two UARTS, three counter-timers, and 256 bytes of register RAM. The EZ-USB family implements I/O differently than the standard 8051 by having its I/O control registers in external memory space. The CY7C64613 preserves this addressing for backward EZ-USB compatibility, and adds the ability to control I/O registers using 8051 Special Function Registers (SFRs). This improves I/O access time. For example, an I/O pin may be toggled using one 8051 instruction, e.g., CPL (bit). The 8051 CODE and XDATA memory consists of an internal 8 KB RAM. This RAM is normally downloaded via the USB cable at plug-in, followed by the 8051 starting up and executing the downloaded code. This gives the CY7C64613 family its "soft" operation feature, whereby permanent memory such as ROM or Flash memory is not required. Program code updates can easily be done in the field since the code is loaded from the PC, not by physically changing or reprogramming a memory device. The 8051 program memory can also be loaded from the EEPROM connected to the I2C compatible bus on reset for stand-alone use without the USB connected. The 128-pin version of the CY7C64613 brings out the full 8051 address and data buses, plus decoded control signals OE#, CS#, RD#, PSEN#, and WR# to allow glueless connection to external memory devices. The 80- and 52-pin packages allow smaller footprints and more cost effective solutions for certain designs, but do not have external access to the 8051 buses.
2.2
USB SIE
The CY7C64613 uses the EZ-USB family enhanced SIE (Serial Interface Engine). This SIE has the intelligence to perform full USB enumeration, creating a default USB device with predefined endpoints and alternate settings. This enhanced SIE is essential in achieving the family's soft operation, since it provides the mechanism to download firmware prior to the 8051 running. Once the 8051 is in control, it can use advanced features of the SIE to simplify its USB firmware. Endpoint zero SETUP data is placed in a separate 8-byte RAM space for easy access. GET_DESCRIPTOR requests are simplified by using a special Setup Data Pointer. The 8051 simply loads a descriptor address into this 16-bit register, and the SIE takes care of the remaining overhead, i.e., dividing the descriptor into packets, sending them via endpoint 0 in response to IN tokens, and providing the necessary handshakes. The 8051 can do other chores while the SIE completes this USB transfer.
2.3
GPIF (General Programmable InterFace)
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite state machine. It allows the CY7C64613 to perform local bus mastering, and can implement a wide variety of protocols such as ATAPI, printer parallel port, PCMCIA and Utopia. The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF instruction defines the state of the control outputs, or determines what state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF instructions make up a single waveform that will be executed to perform the desired data move between the CY7C64613 and the external circuit.
2.4
Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C64613 moves this glue logic into the part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking and bus width conversion. Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its own clock, rather than synchronizing with the clock supplied by the CY7C64613 (24 or 48 MHz). The externally supplied clock Document #: 38-08005 Rev. *B Page 6 of 42
CY7C64613
must be free running. The FIFOs can be controlled either synchronously (using strobe signals and a clock) or asynchronously (using strobe signals only). The slave FIFO data is available as two 8-bit buses, which may be used simultaneously to operate as a single 16-bit data bus. The 16-bit connection, along with fast double-byte mode, combine to give fast conversion between 8- and 16-bit buses. A flexible set of FIFO flags (full, empty, and programmable) provide FIFO flow control.
2.5
DMA
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.6
Flexible Configuration
The EZ-USB FX supports a highly configurable I/O structure. Figure 2-1 on page 8 shows the general scheme of the assignment of pins to I/O ports. The 80- and 56-pin products are subsets of the 128-pin products, hence they follow a similar scheme. For details of how to set the configuration registers to configure the I/O ports, consult "CY7C64613 Pin Descriptions" on page 14 of this data sheet and the EZ-USB FX TRM.
Document #: 38-08005 Rev. *B
Page 7 of 42
Document #: 38-08005 Rev. *B Page 8 of 42
Figure 2-1. General Scheme of Multiplexed Pins for the 128-pin CY7C64613
DISCON# D+ D-
SCL SDA WAKEUP# CLKOUT XIN XOUT RESET#
PA3 / CS# PA2 / OE# PA4 / FWR# / RDY4 / SLWR PA5 / FRD# / RDY5 / SLRD PC6 / WR# / CTL4 PC7 / RD# / CTL5 PSEN# BKPT EA
A[15..0]
D[7..0]
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 X X X X X X X PB[7..0] X X X PD[7..0]
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 X X X X X X X D[7..0] X X X PD[7..0]
ADR0 ADR1 ADR2 ADR3 ADR4 CTL3 CTL4 CTL5 RDY4 RDY5 ADR5 RDY0 RDY2 CTL0 CTL2 GDA[7..0] RDY1 RDY3 CTL1 GDB[7..0]
ADR0 ADR1 ADR2 ADR3 ADR4 CTL3 CTL4 CTL5 RDY4 RDY5 ADR5 RDY0 RDY2 CTL0 CTL2 GDA[7..0] RDY1 RDY3 CTL1 PD[7..0]
BOUTFLAG AINFULL BINFULL AOUTEMTY BOUTEMTY PE5 PE6 PE7 SLWR SLRD X ASEL AOE AINFLAG AOUTFLAG AFI[7..0] BSEL BOE BINFLAG BFI[7..0]
BOUTFLAG AINFULL BINFULL AOUTEMTY BOUTEMTY PE5 PE6 PE7 SLWR SLRD X ASEL AOE AINFLAG AOUTFLAG AFI[7..0] BSEL BOE BINFLAG PD[7..0]
PA0 / T0out PA1 / T1out PA6 / RxD0out PA7 / RxD1out PC0 / RxD0 / RDY0 PC1 / TxD0 / RDY1 PC2 / INT0 PC3 / INT1 / RDY3 PC4 / T0 / CTL1 PC5 / T1 / CTL3
X
X
XCLK
XCLK
XCLK
XCLK
[000] PORTS (Default)
[001] MEMBUS
[110] GPIF 16 bits
[010] GPIF 8 bits
[111] Slave FIFOs 16 bits
[011] Slave FIFOs 8 bits
[nnn] = IFCONFIG[2..0]
CY7C64613
CY7C64613
2.7 Endpoints
Endpoint EP0-IN EP0-OUT EP1-IN EP1-OUT EP2-IN EP2-OUT EP3-IN EP3-OUT EP4-IN EP4-OUT EP5-IN EP5-OUT EP6-IN EP6-OUT EP7-IN EP7-OUT EP8-IN EP8-OUT EP9-IN EP9-OUT EP10-IN EP10-OUT EP11-IN EP11-OUT EP12-IN EP12-OUT EP13-IN EP13-OUT EP14-IN EP14-OUT EP15-IN EP15-OUT Control Control Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Type Buffer Size (Bytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1] 0-1023[1]
The CY7C64613 has 16 Control, Bulk, and Interrupt endpoints. One endpoint pair is dedicated to endpoint zero, with separate EP0-IN and EP0-OUT buffers. Fourteen additional 64-byte buffers may be used as Bulk or Interrupt endpoints. These endpoints may be double-buffered by using an endpoint pairing mechanism. Double buffering allows the 8051 to access a packet as another packet is being transmitted or received over USB. This technique is essential in high-bandwidth applications where NAKs by the USB device would reduce performance. The CY7C64613 also has sixteen Isochronous (ISO) endpoints which share 1024 bytes of double-buffered endpoint memory (2 KB total). The ISO buffer sizes are programmable in 16-byte increments. The Isochronous endpoint buffers are accessed as FIFOs. Endpoint data is serviced either directly by the 8051, or moved on- or off-chip using the built in DMA controller. Bulk data is visible either in 64-byte random access buffers, or as FIFOs (using the AutoPointer feature). Each endpoint has its own interrupt vector, allowing ISRs (Interrupt Service Routines) to be called automatically, with minimum overhead and latency.
Note: 1. A total of 1024 FIFO bytes can be divided among all Isochronous endpoints. (1023 is the maximum USB-specified Isochronous Full-speed packet size.)
Document #: 38-08005 Rev. *B
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CY7C64613
2.8 Default USB Machine
When the CY7C64613 is plugged into the USB with no EEPROM attached to its I2C compatible port (but with the SCL and SDA pull-ups installed), the intelligent SIE enumerates as a generic USB device with the following characteristics. ID Bytes VID (Vendor ID) PID (Product ID) DID (Device ID) Default Endpoints Endpoint Type Alternate Setting 0 0 1 IN 2 IN 2 OUT 4 IN 4 OUT 6 IN 6 OUT 8 IN 8 OUT 9 IN 9 OUT 10 IN 10 OUT CTL INT BULK BULK BULK BULK BULK BULK ISO ISO ISO ISO ISO ISO 64 0 0 0 0 0 0 0 0 0 0 0 0 0 1 64 16 64 64 64 64 64 64 16 16 16 16 16 16 2 64 64 64 64 64 64 64 64 256 256 16 16 16 16 Max Packet Size (bytes) 0547h 2235h 0000h
2.9
IBN (In-Bulk-NAK) Interrupts
The CY7C64613 has a special interrupt called In-Bulk-NAK. IBN is triggered when an IN token has been received by an endpoint (the host is attempting to read data), but the SIE has NAK'd the host (because there is no data in the endpoint). The 8051 program can identify which endpoint triggered the interrupt by reading the IBNIRQ register, where a bit is set for the endpoint (EP1-IN to EP7-IN) that caused the NAK.
Document #: 38-08005 Rev. *B
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CY7C64613
3.0
3.1
Pins
Pin Diagrams
PC3 / INT 1# / RDY3 PC0 / RxD0 / RDY0 PC1 / T xD0 / RDY1 PC6 / WR# / CT L 4 PC7 / RD# / CT L 5 CT L 0 / AINFL AG 41 PC5 / T 1 / CT L 3 PC4 / T 0 / CT L 1
RDY2 / AOE
PC2 / INT 0#
GND
GND
52
51
50
49
48
47
46
45
44
43
42
VCC SCL SDA WAKEUP# AVCC XIN XOUT AGND RESERV ED PA4 / FWR# / RDY4 / SLWR PA5 / FRD# / RDY5 / SLRD CLKOUT GND
1 2 3 4 5 6 7 8 9 10 11 12 13
40
VCC
39 38 37 36 35
GND XCLK CTL2 / AOUTFLAG PB7 / T2OUT / D[7] / GDA[7] / AFI[7] PB6 / INT6 / D[6] / GDA[6] / AFI[6] PB5 / INT5# / D[5] / GDA[5] / AFI[5] PB4 / INT4 / D[4] / GDA[4] / AFI[4] PB3 / TxD1 / D[3] / GDA[3] / AFI[3] PB2 / RxD1 / D[2] / GDA[2] / AFI[2] PB1 / T2EX / D[1] / GDA[1] / AFI[1] PB0 / T2 / D[0] / GDA[0] / AFI[0] RESET# VCC
52 PQFP 10 x 10 mm
34 33 32 31 30 29 28 27
14
15
16
17
18
19
20
21
22
23
24
25 USBD+
XCL KSEL
RESERV ED
RESERV ED
DISCON#
RESERV ED
RESERV ED
RESERV ED
RESERV ED
USBD-
VCC
GND
Figure 3-1. CY7C64613 52-pin PQFP Assignment
Document #: 38-08005 Rev. *B
GND
26
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CY7C64613
3.1 Pin Diagrams (continued)
PC 3 / IN T 1# / R D Y3 PC 0 / R xD 0 / R D Y0 PC 1 / T xD 0 / R D Y1 PC 6 / W R # / C TL4 PC 7 / R D # / C TL 5 C TL0 / AIN FLAG 62 PC 5 / T 1 / C T L3 PC 4 / T 0 / C T L1
R D Y1 / B SEL
R D Y0 / ASEL 63
R D Y2 / AOE
PC 2 / IN T 0#
GN D
GN D
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
NC
65
64
VC C SC L SD A W AK EU P# AVC C XIN XOU T AGN D R ESER VED GN D PA0 / T0OU T PA1 / T1OU T PA2 / OE# PA3 / C S# PA4 / FW R # / R D Y4 PA5 / F R D # / R D Y5 PA6 / R xD 0OU T PA7 / R xD 1OU T C LK OU T GN D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
61
VC C
60 59 58 57 56 55 54 53 52
GN D XC LK C TL2 / AOU TF LAG C TL1 / B IN FLAG NC PE0 / AD R 0 / B OU TF LAG PB 7 / T2OU T / D [7] / GD A[7] / AFI[7] PB 6 / IN T6 / D [6] / GD A[6] / AFI[6] PB 5 / IN T5# / D [5] / GD A[5] / AFI[5] PB 4 / IN T4 / D [4] / GD A[4] / AFI[4] PB 3 / TxD 1 / D [3] / GD A[3] / AFI[3] PB 2 / R xD 1 / D [2] / GD A[2] / AFI[2] PB 1 / T2EX / D [1] / GD A[1] / AFI[1] PB 0 / T2 / D [0] / GD A[0] / AFI[0] NC NC NC GN D R ESET# VC C
80 P QFP 14 x 14 mm
51 50 49 48 47 46 45 44 43 42 41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38 U SB D -
39 U SB D +
PD 3 / GD B [3] / B F I[3]
PD 4 / GD B [4] / B F I[4]
PD 5 / GD B [5] / B F I[5]
PD 6 / GD B [6] / B F I[6]
PD 0 / GD B [0] / B F I[0]
PD 1 / GD B [1] / B F I[1]
PD 2 / GD B [2] / B F I[2]
PD 7 / GD B [7] / B F I[7]
R ESER VED
R ESER VED
R D Y3 / B OE
XC LK SEL
R D Y5 / SLR D
R D Y4 / SLW R
D ISC ON #
VC C
GN D
Figure 3-2. CY7C64613 80 Pin PQFP Assignment
Document #: 38-08005 Rev. *B
GN D
40
Page 12 of 42
CY7C64613
3.1 Pin Diagrams (continued)
PC 3 / IN T1# / R D Y3 PC 0 / R xD 0 / R D Y0 PC 1 / TxD 0 / R D Y1 PC 6 / W R # / C TL4 PC 7 / R D # / C TL 5 PC 5 / T1 / C TL3 PC 4 / T0 / C TL1
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
A 14 A 15 GN D VC C SC L SD A W A K EU P# D0 D1 D2 D3 GN D D4 D5 D6 D7 VC C A VC C XIN XOU T A GN D R ESER VED GN D ADR5 PA 0 / T0OU T PA 1 / T1OU T PA 2 / 0E# PA 3 / C S# PA 4 / FW R # / R D Y4 / SLW R PA 5 / FR D # / R D Y5 / SLR D PA 6 / R xD 0OU T PA 7 / R xD 1OU T PSEN # C LK OU T GN D VC C R ESER VED XC LK SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
103
R D Y1 / B SEL
R D Y2 / AOE
PC 2 / IN T 0#
GN D
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
VC C
A3
A2
A1
A0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
R D Y0 / A SEL C T L0 / A IN FLA G VC C GN D XC LK C T L2 / A OU TFLA G C T L1 / B IN FLA G PE7 / C TL5 PE6 / C TL4 PE5 / C TL3 PE4 / A D R 4 / B OU TEM TY PE3 / A D R 3 / A OU TEM TY PE2 / A D R 2 / B IN FU L L PE1 / A D R 1 / A IN FU LL PE0 / A D R 0 / B OU TFLA G GN D PB 7 / T2OU T / D [7] / GD A [7] / A FI[7] PB 6 / IN T6 / D [6] / GD A [6] / A F I[6] PB 5 / IN T5# / D [5] / GD A [5] / A FI[5] PB 4 / IN T4 / D [4] / GD A [4] / A F I[4] PB 3 / TxD 1 / D [3] / GD A [3] / A FI[3] PB 2 / R xD 1 / D [2] / GD A [2] / A FI[2] PB 1 / T2EX / D [1] / GD A [1] / A FI[1] PB 0 / T2 / D [0] / GD A [0] / A FI[0] GN D R ESER VED R ESER VED VC C R ESER VED R ESER VED GN D R ESER VED R ESER VED R ESET# VC C GN D U SB D + U SB D -
128 PQFP 14 x 20 mm
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63 PD 6 / GD B [6] / B FI[6]
R D Y3 / B OE
D ISC ON #
B K PT
R D Y4 / SLW R
EA
PD 0 / GD B [0] / B F I[0]
PD 1 / GD B [1] / B F I[1]
PD 2 / GD B [2] / B F I[2]
PD 3 / GD B [3] / B F I[3]
PD 4 / GD B [4] / B F I[4]
PD 5 / GD B [5] / B F I[5]
N O C ON N EC T
N O C ON N EC T
R ESER VED
R ESER VED
R ESER VED
R D Y5 / SL R D
R ESER VED
R ESER VED
Figure 3-3. CY7C64613 128 Pin PQFP Assignment
Document #: 38-08005 Rev. *B
PD 7 / GD B [7] / B FI[7]
GN D
GN D
GN D
VC C
GN D
64
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CY7C64613
3.2 General Notes About the Pin Description Table
1. See the EZ-USB FX TRM: For multiplexed pins, consult the EZ-USB FX TRM (primarily Chapter 4) for details of setting the configuration registers. 2. Multiple Routed Signals: In some cases, an internal signal can be routed to more than one pin. For example, in the 80 and 128-pin packages RDY4 can be routed to any combination of (neither, either or both) pins 15 and 26. 3. Tie Up Unused Inputs: It is important that the recommendations in the Pin Description Table be followed, especially for inputs. Unused CMOS inputs can oscillate if they are left open (floating), which can cause higher power usage and decreased reliability. 4. Tie Up Certain Outputs That Are Initially Inputs: Many alternate functions of the FX multiplexed pins are similar to the WR# alternate functions (see the PC6 / WR# / CTL4 pin below) in the following respect: If WR# is chosen as the function of PC6, it should be pulled up to VCC through a pull-up resistor. This is to ensure that WR# is inactive (pulled HIGH) at power-up, since, before the 8051 can configure this pin to WR#, it defaults to `PC6 an input' (not driven by the FX pin). All multiplexed pins that you use should be carefully considered in your circuit design for the effects of the transition through their default configuration at power-up. These are typically (though not always) active LOW signals such as WR#. The critical time interval to be considered is between RESET# deasserted and the pin driven as an output (immediately after the 8051 code has initialized the port to be an alternate function that it is an output).
3.3
128 18 21 48
CY7C64613 Pin Descriptions
80 5 8 28 52 5 8 18 Name AVCC AGND DISCON# Type Power Power O/Z Default N/A N/A H Description Analog VCC. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. Disconnect. This pin can drive HIGH, LOW, or float. DISCON# pin floats when the register bit USBCS.2 is LOW, and drives when it is HIGH. The drive level of the DISCON# pin is the invert of register bit USBCS.3. The DISCON# pin is normally connected to the USB D+ line through a 1500 resistor. The CY7C64613 signals a USB connection by setting USBCS.3=0 (drive 3.3V) and USBCS.2=1 (output enable). The CY7C64613 signals a USB disconnect by setting USBCS.2=0 which floats the pin and disconnects the 1500 resistor from D+. USB D- Connect to the USB D- signal through a 22 5% ohm resistor. USB D+ Connect to the USB D+ signal through a 22 5% ohm resistor. 8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address. During DMA transfers that use the RD# and WR# strobes, the address bus contains the incrementing DMA source or destination address for data transferred over D[7.0].
65 66 105 106 107 108 114 115 116 117 118 120 121 122 127 128 1 2
38 39
24 25
USBD- USBD+ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
I/O/Z I/O/Z Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
Z Z L L L L L L L L L L L L L L L L
Document #: 38-08005 Rev. *B
Page 14 of 42
CY7C64613
3.3
128 8 9 10 11 13 14 15 16 33
CY7C64613 Pin Descriptions (continued)
80 52 D0 D1 D2 D3 D4 D5 D6 D7 PSEN# Name Type I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Output Default Z Z Z Z Z Z Z Z H Program Store Enable PSEN# strobes LOW when the 8051 fetches a CODE byte from external memory. If EA = 0, the 8051 fetches CODE from external memory from 0x1B40 to 0xFFFF. If EA = 1, the 8051 fetches CODE from external memory from 0x0000 to 0xFFFF. See EA pin. Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the USBBAV register (BPEN=1). If the BPPULSE bit in the USBBAV register is HIGH, BKPT pulses HIGH for eight 24-/48-MHz clocks. If the BPPULSE bit is LOW, BKPT stays HIGH until the 8051 clears the BREAK bit (by writing a 1 to it) in the USBBAV register. Active LOW Reset. This pin resets the entire chip. It is normally tied to VCC through a 10K resistor and to GND through a 1-F capacitor. Hysteresis input. External Access. This pin determines where the 8051 fetches code between addresses 0x0000 and 0x1B3F. If EA=0 the 8051 fetches this code from its internal RAM. If EA=1 the 8051 fetches this code from external memory. (normally used to boot from external memory, for example, boot from Flash). This pin is "live". See PSEN# pin. (EA is tied to GND internally in both the 80- and 52-pin packages.) Description 8051 Data Bus. This bidirectional bus is: - input for bus reads - output for bus writes - high-impedance when inactive. The data bus is active only for external bus accesses, and is driven LOW in suspend. The data bus is used for: - external 8051 program and data memory. - DMA transfers that use the RD#, FRD#, WR#, FWR# pins as strobes.
41
BKPT
Output
L
69
42
28
RESET#
Input
N/A
51
EA
Input
N/A
19
6
6
XIN
Input
N/A
Crystal Input. Connect this signal to a 12-MHz series-resonant, fundamental mode crystal and 22-33 pF capacitor to GND. Also connect a 1-M resistor between XIN and XOUT. It is also correct to drive XIN with an external 12-MHz square wave derived from another clock source.
20
7
7
XOUT
Output
N/A
Crystal Output. Connect this signal to a 12-MHz series-resonant, fundamental mode crystal and 22-33 pF capacitor to GND. Also connect a 1-M resistor between XIN and XOUT. If an external clock is used to drive XIN, leave this pin open.
Document #: 38-08005 Rev. *B
Page 15 of 42
CY7C64613
3.3
128 34
CY7C64613 Pin Descriptions (continued)
80 19 52 12 Name CLKOUT Type O/Z Default Description 24 MHz Clock Output. This is the 24- or 48-MHz clock, the master clock for the 8051, phase locked to the 12-MHz XIN/XOUT clock. (Note: the GPIF always uses a 48-MHz clock or XCLK, regardless of the 8051 clock. See XCLK and XCLKSEL.) The frequency of the 8051 clock is set via a boot EEPROM bit: If Config 0.2 = 0, CLKOUT is 24 MHz. If Config 0.2 = 1, CLKOUT is 48 MHz. CLKOUT may be inverted by setting a boot EEPROM bit CONFIG0.1 = 1. If no EEPROM is connected to the I2C compatible port (the required pull-up resistors must be present), the Config0 bits default to zero, hence - CLKOUT is 24 MHz - CLKOUT is non-inverted. The 8051 may three-state this output by setting CPUCS.1 = 1. I (PA0) Multiplexed pin whose function is selected by two bits: PORTACFG.0 and IFCONFIG.3. PA0 is a bidirectional IO port pin. T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows. Multiplexed pin whose function is selected by two bits: PORTACFG.1 and IFCONFIG.3. PA1 is a bidirectional IO port pin. T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows. Multiplexed pin whose function is selected by two bits: PORTACFG.2 and IFCONFIG.3. PA2 is a bidirectional IO port pin. OE# is an active-LOW output enable for external memory. If the OE# function is chosen for this pin, it should be externally pulled up to VCC through a pull-up resistor. This is to ensure that OE# is inactive (pulled HIGH) at power up, since, before the 8051 can configure this pin to OE#, it defaults to `PA2 an input' Multiplexed pin whose function is selected by the PORTACFG.3 bit. PA3 is a bidirectional I/O port pin. CS# is an active-LOW chip select for external memory. If the CS# function is chosen for this pin, it should be externally pulled up to VCC. This is to ensure that CS# is inactive (pulled HIGH) at power up, since, before the 8051 can configure this pin to CS#, it defaults to `PA3 an input'. Multiplexed pin whose function is selected by the following bits: PORTACFG.4, PORTACF2.4, and IFCONFIG[1..0]. PA4 is a bidirectional I/O port pin. FWR# is the write strobe output for an external FIFO connected to the data bus D[7..0]. RDY4 is a GPIF input signal. RDY4 is a GPIF input signal. SLWR is the write strobe input for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. If the FWR# pin is used, it should be externally pulled up to VCC. This is to ensure that FWR# is inactive (pulled HIGH) at power up, since, before the 8051 can configure this pin to FWR#, it defaults to `PA4 an input'. Page 16 of 42
Port A 25 11 PA0 or T0OUT I/O/Z
26
12
PA1 or T1OUT
I/O/Z
I (PA1)
27
13
PA2 or OE# or
I/O/Z
I (PA2)
28
14
PA3 or CS#
I/O/Z
I (PA3)
29
15
10
PA4 or FWR# or RDY4 or SLWR
I/O/Z
I (PA4)
Document #: 38-08005 Rev. *B
CY7C64613
3.3
128 30
CY7C64613 Pin Descriptions (continued)
80 16 52 11 Name PA5 or FRD# or RDY5 or SLRD Type I/O/Z Default I (PA5) Description Multiplexed pin whose function is selected by the following bits: PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0]. PA5 is a bidirectional I/O port pin. FRD# is the write strobe output for an external FIFO connected to the data bus D[7..0]. RDY5 is a GPIF input signal. SLRD is the read strobe input for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. If the FRD# pin is used, it should be externally pulled up to VCC. This is to ensure that FRD# is inactive (pulled HIGH) at power up, since, before the 8051 can configure this pin to FRD#, it defaults to `PA5 an input'. Multiplexed pin whose function is selected by the PORTACFG.6 bit. PA6 is a bidirectional I/O port pin. RxD0OUT is an active-HIGH signal from 8051 UART0. If RxD0OUT is selected and UART0 is in mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1. Multiplexed pin whose function is selected by the PORTACFG.7 bit. PA7 is a bidirectional I/O port pin. RxD1OUT is an active-HIGH output from 8051 UART1. When RxD1OUT is selected and UART1 is in mode 0, this pin provides the output data for UART1 only when it is in sync mode. In modes 1, 2, and 3, this pin is HIGH. The following descriptions apply to the PORT B pins: D[7..0] is the bidirectional 8051 data bus. GDA[7..0] is the bidirectional GPIF A data bus. AFI[7..0] is the bidirectional A-FIFO data bus.
31
17
PA6 or RxD0OUT
I/O/Z
I (PA6)
32
18
PA7 or RxD1OUT
I/O/Z
I (PA7)
Port B
79
47
29
PB0 or T2 or D[0] or GDA[0] or AFI [0]
I/O/Z
I (PB0)
Multiplexed pin whose function is selected by the following bits: PORTBCFG.0 and IFCONFIG[1..0]. PB0 is a bidirectional I/O port pin. T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does not use this pin. D[0] is the bidirectional 8051 data bus, bit 0. GDA[0] is the bidirectional GPIF A data bus, bit 0. AFI [0] is the bidirectional A-FIFO data bus, bit 0. Multiplexed pin whose function is selected by the following bits: PORTBCFG.1 and IFCONFIG[1..0]. PB1 is a bidirectional I/O port pin. T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON. D[1] is the bidirectional 8051 data bus, bit 1. GDA[1] is the bidirectional GPIF A data bus, bit 1. AFI [1] is the bidirectional A-FIFO data bus, bit 1. Multiplexed pin whose function is selected by the following bits: PORTBCFG.2 and IFCONFIG[1..0]. PB2 is a bidirectional I/O port pin. RxD1 is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes. D[2] is the bidirectional 8051 data bus, bit 2. GDA[2] is the bidirectional GPIF A data bus, bit 2. AFI [2] is the bidirectional A-FIFO data bus, bit 2.
80
48
30
PB1 or T2EX or D[1] or GDA[1] or AFI [1]
I/O/Z
I (PB1)
81
49
31
PB2 or RxD1 or D[2] or GDA[2] or AFI [2]
I/O/Z
I (PB2)
Document #: 38-08005 Rev. *B
Page 17 of 42
CY7C64613
3.3
128 82
CY7C64613 Pin Descriptions (continued)
80 50 52 32 Name PB3 or TxD1 or D[3] or GDA[3] or AFI [3] Type I/O/Z Default I (PB3) Description Multiplexed pin whose function is selected by the following bits: PORTBCFG.3 and IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. TxD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. D[3] is the bidirectional 8051 data bus, bit 3. GDA[3] is the bidirectional GPIF A data bus, bit 3. AFI [3] is the bidirectional A-FIFO data bus, bit 3. Multiplexed pin whose function is selected by the following bits: PORTBCFG.4 and IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. INT4 is the 8051 INT4 interrupt request input signal. The INT4 interrupt is triggered on the rising edge of this input signal. D[4] is the bidirectional 8051 data bus, bit 4. GDA[4] is the bidirectional GPIF A data bus, bit 4. AFI [4] is the bidirectional A-FIFO data bus, bit 4. Multiplexed pin whose function is selected by the following bits: PORTBCFG.5 and IFCONFIG[1..0]. PB5 is a bidirectional I/O port pin. INT5# is the 8051 INT5 interrupt request input signal. The INT5 interrupt is triggered on the falling edge of this input signal. D[5] is the bidirectional 8051 data bus, bit 5. GDA[5] is the bidirectional GPIF A data bus, bit 5. AFI [5] is the bidirectional A-FIFO data bus, bit 5. Multiplexed pin whose function is selected by the following bits: PORTBCFG.6 and IFCONFIG[1..0]. PB6 is a bidirectional I/O port pin. INT6 is the 8051 INT5 interrupt request input signal. The INT6 interrupt is triggered on the rising edge of this input signal. D[6] is the bidirectional 8051 data bus, bit 6. GDA[6] is the bidirectional GPIF A data bus, bit 6. AFI [6] is the bidirectional A-FIFO data bus, bit 6. Multiplexed pin whose function is selected by the following bits: PORTBCFG.7 and IFCONFIG[1..0]. PB7 is a bidirectional I/O port pin. T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows. D[7] is the bidirectional 8051 data bus, bit 7. GDA[7] is the bidirectional GPIF A data bus, bit 7. AFI [7] is the bidirectional A-FIFO data bus, bit 7. Multiplexed pin whose function is selected by the PORTCCFG.0 and PORTCGPIF.0 bits. PC0 is a bidirectional I/O port pin. RxD0 is the active-HIGH RxD0 input to 8051 UART0, which provides data to the UART in all modes. RDY0 is a GPIF input signal. Multiplexed pin whose function is selected by the PORTCCFG.1 and PORTCGPIF.1 bits. PC1 is a bidirectional I/O port pin. TxD0 is the active-HIGH TxD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. RDY1 is a GPIF input signal. Multiplexed pin whose function is selected by the PORTCCFG.2 bit. PC2 is a bidirectional I/O port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). Page 18 of 42
83
51
33
PB4 or INT4 or D[4] or GDA[4] or AFI [4]
I/O/Z
I (PB4)
84
52
34
PB5 or INT5# or D[5] or GDA[5] or AFI [5]
I/O/Z
I (PB5)
85
53
35
PB6 or INT6 or D[6] or GDA[6] or AFI [6]
I/O/Z
I (PB6)
86
54
36
PB7 or T2OUT or D[7] or GDA[7] or AFI [7]
I/O/Z
I (PB7)
Port C 110 68 43 PC0 or RxD0 or RDY0 I/O/Z I (PC0)
111
69
44
PC1 or TxD0 or RDY1
I/O/Z
I (PC1)
112
70
45
PC2 or INT0#
I/O/Z
I (PC2)
Document #: 38-08005 Rev. *B
CY7C64613
3.3
128 113
CY7C64613 Pin Descriptions (continued)
80 71 52 46 Name PC3 or INT1# or RDY3 Type I/O/Z Default I (PC3) Description Multiplexed pin whose function is selected by the: PORTCCFG.3 and PORTCGPIF.3 bits. PC3 is a bidirectional I/O port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). RDY3 is a GPIF input signal. Multiplexed pin whose function is selected by the PORTCCFG.4 and PORTCGPIF.4 bits. PC4 is a bidirectional I/O port pin. T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit. CTL1 is a GPIF output signal. Multiplexed pin whose function is selected by the PORTCCFG.5 and PORTCGPIF.5 bits. PC5 is a bidirectional I/O port pin. T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit. CTL3 is a GPIF output signal. Multiplexed pin whose function is selected by the PORTCCFG.6 and PORTCGPIF.6 bits. PC6 is a bidirectional I/O port pin. WR# is the active-LOW write strobe output for external memory. CTL4 is a GPIF output signal. This is to ensure that WR# is inactive (pulled high) at power up. Before the 8051 can configure this pin to WR#, it defaults to `PC6 an input' Multiplexed pin whose function is selected by the PORTCCFG.7 and PORTCGPIF.7 bits. PC7 is a bidirectional I/O port pin. RD# is the active-LOW read strobe output for external memory. CTL5 is a GPIF output signal. This is to ensure that RD# is inactive (pulled high) at power up. Before the 8051 can configure this pin to RD#, it defaults to `PC6 an input'. Port D is multiplexed between three sources: PD0-PD7 are bidirectional I/O port pins. GDB[7..0] is the GPIF B data bus. BFI[7..0] is the bidirectional B-FIFO data bus.
123
73
48
PC4 or T0 or CTL1
I/O/Z
I (PC4)
124
74
49
PC5 or T1 or CTL3
I/O/Z
I (PC5)
125
75
50
PC6 or WR# or CTL4
I/O/Z
I (PC6)
126
76
51
PC7 or RD# or CTL5
I/O/Z
I (PC7)
Port D
56
30
PD0 or GDB[0] or BFI [0] PD1 or GDB[1] or BFI [1] PD2 or GDB[2] or BFI [2] PD3 or GDB[3] or BFI [3] PD4 or GDB[4] or BFI [4]
I/O/Z
I (PD0) I (PD1) I (PD2) I (PD3) I (PD4)
Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [0] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [1] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [2] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [3] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [4] is the bidirectional B-FIFO data bus.
57
31
I/O/Z
58
32
I/O/Z
59
33
I/O/Z
60
34
I/O/Z
Document #: 38-08005 Rev. *B
Page 19 of 42
CY7C64613
3.3
128 61
CY7C64613 Pin Descriptions (continued)
80 35 52 Name PD5 or GDB[5] or BFI [5] PD6 or GDB[6] or BFI [6] PD7 or GDB[7] or BFI [7] PE0 or ADR0 or BOUTFLAG Type I/O/Z Default I (PD5) I (PD6) I (PD7) Description Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [5] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [6] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [7] is the bidirectional B-FIFO data bus.
63
36
I/O/Z
64
37
I/O/Z
Port E 88 I/O/Z I (PE0) Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE0 is a bidirectional I/O port pin. ADR0 is a GPIF address output pin. BOUTFLAG is the B-OUT FIFO flag output, which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE1 is a bidirectional I/O port pin. ADR1 is a GPIF address output pin. AINFULL is the A-IN FIFO flag output, which indicates FIFO full. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE2 is a bidirectional I/O port pin. ADR2 is a GPIF address output pin. BINFULL is the B-IN FIFO flag output, which indicates FIFO full. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE3 is a bidirectional I/O port pin. ADR3 is a GPIF address output pin. AOUTEMTY is the A-OUT FIFO flag output, which indicates FIFO empty. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE4 is a bidirectional I/O port pin. ADR4 is a GPIF address output pin. BOUTEMTY is the B-OUT FIFO flag output, which indicates FIFO empty. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE5 is a bidirectional I/O port pin. CTL3 is a GPIF output signal. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE6 is a bidirectional I/O port pin. CTL4 is a GPIF output signal. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE7 is a bidirectional I/O port pin. CTL5 is a GPIF output signal. ADR5 is a GPIF address output pin. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY0 is a GPIF input signal. ASEL is the select input for the A-IN and A-OUT FIFOs. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY1 is a GPIF input signal. BSEL is the select input for the B-IN and B-OUT FIFOs.
89
PE1 or ADR1 or AINFULL PE2 or ADR2 or BINFULL PE3 or ADR3 or AOUTEMTY
I/O/Z
I (PE1)
90
I/O/Z
I (PE2)
91
I/O/Z
I (PE3)
92
PE4 or ADR4 or BOUTEMTY
I/O/Z
I (PE4)
93
PE5 or CTL3
I/O/Z
I (PE5)
94
PE6 or CTL4
I/O/Z
I (PE6)
95
PE7 or CTL5
I/O/Z
I (PE7)
24 102 63
ADR5 RDY0 or ASEL
O Input
X X
103
64
RDY1 or BSEL
Input
X
Document #: 38-08005 Rev. *B
Page 20 of 42
CY7C64613
3.3
128 104
CY7C64613 Pin Descriptions (continued)
80 65 52 42 Name RDY2 or AOE Type Input Default X Description Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY2 is a GPIF input signal. AOE is the output enable input for the A-OUT FIFO. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY3 is a GPIF input signal. BOE is the output enable input for the B-OUT FIFO. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY4 is a GPIF input signal. SLWR is the input-only write strobe for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY5 is a GPIF input signal. SLRD is the input-only read strobe for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. AINFLAG is the A-IN FIFO flag output which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. BINFLAG is the B-IN FIFO flag output which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL2 is a GPIF control output. AOUTFLAG is the A-OUT FIFO flag output which indicates a programmable level of FIFO fullness. External clock input, used for synchronously clocking data into the slave FIFOs. XCLK also serves as a timing reference for all slave FIFO control signals and GPIF. This clock must be free - running. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Must be left open. Reserved. Connect to Ground. Reserved. Connect to 3.3V power source. USB Wakeup. If the 8051 is in suspend, a HIGH-to-LOW edge on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP# LOW inhibits the EZ-USB chip from suspending. I2C-compatible Clock. Connect to VCC with a 1K resistor, even if no I2C-compatible peripheral is attached. Page 21 of 42
44
25
RDY3 or BOE
Input
X
45
26
RDY4 or SLWR
Input
X
46
27
RDY5 or SLRD
Input
X
101
62
41
CTL0 or AINFLAG
Output
X
96
57
CTL1 or BINFLAG
Output
X
97
58
37
CTL2 or AOUTFLAG
Output
X
98
59
38
XCLK
Input
N/A
53 54 70 71 73 74 76 77 50 49
22 23
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Input
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
20 19
Reserved Reserved Reserved WAKEUP#
7
4
4
5
2
2
SCL
Open Drain
Z
Document #: 38-08005 Rev. *B
CY7C64613
3.3
128 6 38 39 37 22 4 17 36 55 68 75 100 109 3 12 23 35 40 47 52 62 67 72 78 87 99 119 42 43 60 72 79 44 45 46 55 56 66 67 77 78 39 47 40 43 26 29 21 10 20 13 80 52 61 40 41 27 21 14
CY7C64613 Pin Descriptions (continued)
80 3 23 24 22 9 1 52 3 16 17 15 9 1 Name SDA XCLKSEL Reserved Reserved Reserved VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC Type Open Drain Input Rsrvd Rsrvd Rsrvd Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Default Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description I2C-compatible Data. Connect to VCC with a 1K resistor, even if no I2C-compatible peripheral is attached. HIGH: Use XCLK pin for GPIF and slave FIFOs. LOW: Use internal 48-MHz clock for GPIF and slave FIFOs. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open.
Document #: 38-08005 Rev. *B
Page 22 of 42
CY7C64613
4.0
Addr
Register Summary
Name FIFO A-IN Description D7 D6 D5 D4 D3 D2 D1 D0
7800 AINDATA 7801 AINBC 7802 AINPF 7803 AINPFPIN 7804 (reserved)
FIFO B-IN
Read Data from FIFO A Input FIFO A Byte Count FIFO A-IN Programmable Flag (internal bit) FIFO A-IN Prorammable Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
7805 BINDATA 7806 BINBC 7807 BINPF 7808 BINPFPIN 7809 (reserved)
Read Data from FIFO B Input FIFO B Byte Count FIFO B-IN Programmable Flag (internal bit) FIFO B-IN Programmable Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
FIFO A/B-IN Control
780A ABINCS 780B ABINIE 780C ABINIRQ 780D (reserved)
FIFO A-OUT
Input FIFOs Toggle control and flags Input FIFO Interrupt Enables Input FIFO Interrupt Requests
INTOG 0 0
INSEL 0 0
AINPF
AINEF
AINFF AINFFIE
BINPF
BINEF
BINFF BINFFIE
AINPFIE AINEFIE
BINPFIE BINEFIE
AINPFIR AINEFIR AINFFIR BINPFIR BINEFIR BINFFIR
780E AOUTDATA 780F AOUTBC 7810 AOUTPF 7811 AOUTPFPIN 7812 (reserved)
FIFO B-OUT
Load Output FIFO A Output FIFO A Byte Count FIFO A-OUT Programmable Flag (internal bit) FIFO A-OUT Programmable Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
7813 BOUTDATA 7814 BOUTBC 7815 BOUTPF 7816 BOUTPFPIN 7817 (reserved)
Load Output FIFO B Output FIFO B Byte Count FIFO B-OUT Programmable (internal bit) FIFO B-OUT Programmable Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
FIFO A/B OUT Control
7818 ABOUTCS 7819 ABOUTIE 781A ABOUTIRQ 781B (reserved)
Output FIFOs Toggle control and flags Output FIFO Interrupt Enables Output FIFO Interrupt Requests
OUTTOG OUTSEL AOUTPF AOUTEF AOUTFF BOUTPF BOUTEF BOUTFF 0 0 0 0 AOUTPFIE AOUTPFIR AOUTEFIE AOUTEFIR AOUTFFIE AOUTFFIR BOUTPFIE BOUTPFIR BOUTEFIE BOUTEFIR BOUTFFIE BOUTFFIR
FIFO A/B Global Control
781C ABSETUP 781D ABPOLAR 781E ABFLUSH
FIFO Setup FIFO Control Signals Polarity Write (data=x) to reset all flags
0 0 *[2]
0 0 *
ASYNC BOE *
DBLIN AOE *
0 SLRD *
OUTDLY SLWR *
0 ASEL *
DBLOUT BSEL *
Document #: 38-08005 Rev. *B
Page 23 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name Description D7 D6 D5 D4 D3 D2 D1 D0
781F-7823 (reserved) 7824 WFSELECT 7825 IDLECS 7826 IDLECTLOUT 7827 CTLOUTCFG 7828-7829 (reserved) 782A GPIFADRL 782B (reserved) 782C AINTC 782D AOUTTC 782E ATRIG 782F (reserved) 7830 BINTC 7831 BOUTTC 7832 BTRIG 7833 (reserved) 7834 SGLDATH 7836 SGLDATLNTRIG 7837(reserved) 7838 READY 7839 ABORT 783A (reserved) 783B GENIE 783C GENIRQ 783D-7840 (reserved) IO Ports D, E 7841 OUTD 7842 PINSD 7843 OED 7844 (reserved) 7845 OUTE 7846 PINSE 7847 OEE 7848 (reserved) 7849 PORTSETUP Timer0 Clock source, Port-to-SFR mapping 0 0 0 0 0 0 T0CLK SFRPORT Output Port E Input Port E pins Port E Output Enable OUTE7 PINE7 OEE7 OUTE6 PINE6 OEE6 OUTE5 PINE5 OEE5 OUTE4 PINE4 OEE4 OUTE3 PINE3 OEE3 OUTE2 PINE2 OEE2 OUTE1 PINE1 OEE1 OUTE0 PINE0 OEE0 Output Port D Input Port D pins Port D Output Enable OUTD7 PIND7 0ED7 OUTD6 PIND6 0ED6 OUTD5 PIND5 0ED5 OUTD4 PIND4 0ED4 OUTD3 PIND3 0ED3 OUTD2 PIND2 0ED2 OUTD1 PIND1 0ED1 OUTD0 PIND0 0ED0 GPIF/DMA Interrupt Enable GPIF/DMA Interrupt Request 0 0 0 0 0 0 0 0 0 0 DMADN DMADN GPWR GPWR GPDONE GPDONE GPIF Ready flags Abort current GPIF cycle INTRDY * SAS * RDY5 * RDY4 * RDY3 * RDY2 * RDY1 * RDY0 * GPIF Data High GPIF Data Low and No Trigger D15 D7 D7 D14 D6 D6 D13 D5 D5 D12 D4 D4 D11 D3 D3 D10 D2 D2 D9 D1 D1 D8 D0 D0 7835 SGLDATLTRIG GPIF Data Low and Trigger FIFO B In Transfer Count FIFO B Out Transfer Count Trigger a FIFO B RD/WR FITC FITC * * * * Transfer Count Transfer Count * * * * FIFO A In Transfer Count FIFO A Out Transfer Count Trigger a FIFO A RD/WR FITC FITC * * * * Transfer Count Transfer Count * * * * GPIF Address * * ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Waveform Selector GPIF IDLE State control GPIF IDLE CTL states GPIF CTL Drive mode SINGLEWR DONE IOE3 TRICTL 0 IOE2 0 SINGLERD 0 IOE1/ CTL5 CTL5 0 IOE0/ CTL4 CTL4 0 CTL3 CTL3 FIFOWR 0 CTL2 CTL2 0 CTL1 CTL1 FIFORD IDLEDRV CTL0 CTL0
Note: 2. Register bit is not used and undefined if read.
784A IFCONFIG 784B PORTACF2 784C PORTCCF2 784D-784E (reserved)
DMA Control
Select 8/16 bit data bus, configure buses (IF) Port A Configuration #2 Port C Configuration #2
52ONE 0 CTL5
0 0 CTL4
0 SLRD CTL3
0 SLWR CTL1
GSTATE 0 RDY3
BUS16 0 0
IF1 0 RDY1
IF0 0 RDY0
784F DMASRCH 7850 DMASRCL
DMA Source H DMA Source L
A15 A7
A14 A6
A13 A5
A12 A4
A11 A3
A10 A2
A9 A1
A8 A0
Document #: 38-08005 Rev. *B
Page 24 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name Description D7 D6 D5 D4 D3 D2 D1 D0
7851 DMADESTH 7852 DMADESTL 7853 (reserved) 7854 DMALEN 7855 DMAGO 7856 (reserved) 7857 DMABURST 7858 DMAEXTFIFO 7859 - 785C (reserved) 785D INT4IVEC 785E INT4SETUP 785F-78FF (reserved) 7900- WFDESC 797F 7980-7B3F (reserved)
DMA Destination H DMA Destination L DMA Transfer Length Start DMA Transfer DMA Burst control Dummy data reg for using RAM as external FIFO Interrupt 4 Vector Interrupt 4 Set-up
A15 A7 D7 DONE * n/a
A14 A6 D6 * * n/a
A13 A5 D5 * * n/a
A12 A4 D4 * DSTR2 n/a
A11 A3 D3 * DSTR1 n/a
A10 A2 D2 * DSTR0 n/a
A9 A1 D1 * RB n/a
A8 A0 D0 * WB n/a
0 0
1 0
I4V3 0
I4V2 0
I4V1 0
I4V0 INT4SFC
0 INTERNAL
0 AV4EN
GPIF Waveform Descriptors
Endpoint 0-7 Data Buffers
7B40 OUT7BUF 7B80 IN7BUF 7BC0 OUT6BUF 7C00 IN6BUF 7C40 OUT5BUF 7C80 IN5BUF 7CC0 OUT4BUF 7D00 IN4BUF 7D40 OUT3BUF 7D80 IN3BUF 7DC0 OUT2BUF 7E00 IN2BUF 7E40 OUT1BUF 7E80 IN1BUF 7EC0 OUT0BUF 7F00 IN0BUF 7F40-7F5F (reserved)
(64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes)
d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7
d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6
d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5
d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4
d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3
d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2
d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1
d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0
Isochronous Data
7F60 OUT8DATA 7F61 OUT9DATA 7F62 OUT10DATA 7F63 OUT11DATA 7F64 OUT12DATA 7F65 OUT13DATA 7F66 OUT14DATA 7F67 OUT15DATA 7F68 IN8DATA 7F69 IN9DATA 7F6A IN10DATA 7F6B IN11DATA
Endpoint 8 OUT Data Endpoint 9 OUT Data Endpoint 10 OUT Data Endpoint 11 OUT Data Endpoint 12 OUT Data Endpoint 13 OUT Data Endpoint 14 OUT Data Endpoint 15 OUT Data Endpoint 8 IN Data Endpoint 9 IN Data Endpoint 10 IN Data Endpoint 11 IN Data
d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7
d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6
d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5
d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4
d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3
d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2
d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1
d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0
Document #: 38-08005 Rev. *B
Page 25 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name Description D7 D6 D5 D4 D3 D2 D1 D0
7F6C IN12DATA 7F6D IN13DATA 7F6E IN14DATA 7F6F IN15DATA 7F70 OUT8BCH 7F71 OUT8BCL 7F72 OUT9BCH 7F73 OUT9BCL 7F74 OUT10BCH 7F75 OUT10BCL 7F76 OUT11BCH 7F77 OUT11BCL 7F78 OUT12BCH 7F79 OUT12BCL 7F7A OUT13BCH 7F7B OUT13BCL 7F7C OUT14BCH 7F7D OUT14BCL 7F7E OUT15BCH 7F7F OUT15BCL 7F80-7F91 (reserved)
CPU Registers
Endpoint 12 IN Data Endpoint 13 IN Data Endpoint 14 IN Data Endpoint 15 IN Data EP8 Out Byte Count H EP8 Out Byte Count L EP9 Out Byte Count H EP9 Out Byte Count L EP10 Out Byte Count H EP10 Out Byte Count L EP11 Out Byte Count H EP11 Out Byte Count L EP12 Out Byte Count H EP12 Out Byte Count L EP13 Out Byte Count H EP13 Out Byte Count L EP14 Out Byte Count H EP14 Out Byte Count L EP15 Out Byte Count H EP15 Out Byte Count L
d7 d7 d7 d7 0 d7 0 d7 0 d7 0 d7 0 d7 0 d7 0 d7 0 d7
d6 d6 d6 d6 0 d6 0 d6 0 d6 0 d6 0 d6 0 d6 0 d6 0 d6
d5 d5 d5 d5 0 d5 0 d5 0 d5 0 d5 0 d5 0 d5 0 d5 0 d5
d4 d4 d4 d4 0 d4 0 d4 0 d4 0 d4 0 d4 0 d4 0 d4 0 d4
d3 d3 d3 d3 0 d3 0 d3 0 d3 0 d3 0 d3 0 d3 0 d3 0 d3
d2 d2 d2 d2 0 d2 0 d2 0 d2 0 d2 0 d2 0 d2 0 d2 0 d2
d1 d1 d1 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1
d0 d0 d0 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0
Isochronous Byte Counts
7F92 CPUCS 7F93 PORTACFG 7F94 PORTBCFG 7F95 PORTCCFG 7F96 OUTA 7F97 OUTB 7F98 OUTC 7F99 PINSA 7F9A PINSB 7F9B PINSC 7F9C OEA 7F9D OEB 7F9E OEC 7F9F (reserved)
Control & Status Port A Configuration Port B Configuration Port C Configuration Output Register A Output Register B Output Register C Port Pins A Port Pins B Port Pins C Output Enable A Output Enable B Output Enable C
rv3 RxD1out T2OUT RD OUTA7 OUTB7 OUTC7 PINA7 PINB7 PINC7 OEA7 OEB7 OEC7
rv2 RxD0out INT6 WR OUTA6 OUTB6 OUTC6 PINA6 PINB6 PINC6 OEA6 OEB6 OEC6
rv1 FRD INT5 T1 OUTA5 OUTB5 OUTC5 PINA5 PINB5 PINC5 OEA5 OEB5 OEC5
rv0 FWR INT4 T0 OUTA4 OUTB4 OUTC4 PINA4 PINB4 PINC4 OEA4 OEB4 OEC4
24/48 CS TxD1 INT1 OUTA3 OUTB3 OUTC3 PINA3 PINB3 PINC3 OEA3 OEB3 OEC3
CLKINV OE RxD1 INT0 OUTA2 OUTB2 OUTC2 PINA2 PINB2 PINC2 OEA2 OEB2 OEC2
CLKOUT 8051RES OE T1out T2EX TxD0 OUTA1 OUTB1 OUTC1 PINA1 PINB1 PINC1 OEA1 OEB1 OEC1 T0out T2 RxD0 OUTA0 OUTB0 OUTC0 PINA0 PINB0 PINC0 OEA0 OEB0 OEC0
Input-Output Port Registers
Isochronous Control/Status Registers
7FA0 ISOERR 7FA1 ISOCTL 7FA2 ZBCOUT 7FA3 (reserved) 7FA4 (reserved)
ISO OUT Endpoint Error Isochronous Control Zero Byte Count bits
ISO15 ERR * EP15
ISO14 ERR * EP14
ISO13 ERR * EP13
ISO12 ERR * EP12
ISO11 ERR PPSTAT EP11
ISO10 ERR MBZ EP10
ISO9 ERR MBZ EP9
ISO8 ERR ISODISAB EP8
I2C compatible Registers
Document #: 38-08005 Rev. *B
Page 26 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name Description D7 D6 D5 D4 D3 D2 D1 D0
7FA5 I2CS 7FA6 I2DAT 7FA7 I2CMODE
Interrupts
Control & Status Data STOP Int Enable, patible bus speed Interrupt Vector EPIN Interrupt Request EPOUT Interrupt Request USB Interrupt Request EP0-7IN Int Enables EP0-7OUT Int Enables USB Int Enables Breakpoint & Autovector IN-Bulk-NAK Intr. Request IN-Bulk-NAK Intr. enable Breakpoint Address H Breakpoint Address L Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count I2C com-
START d7 0
STOP d6 0
LASTRD d5 0
ID1 d4 0
ID0 d3 0
BERR d2 0
ACK d1 STOPIE
DONE d0 400KHZ
7FA8 IVEC 7FA9 IN07IRQ 7FAA OUT07IRQ 7FAB USBIRQ 7FAC IN07IEN 7FAD OUT07IEN 7FAE USBIEN 7FAF USBBAV 7FB0 IBNIRQ 7FB1 IBNIEN 7FB2 BPADDRH 7FB3 BPADDRL 7FB4 EP0CS 7FB5 IN0BC 7FB6 IN1CS 7FB7 IN1BC 7FB8 IN2CS 7FB9 IN2BC 7FBA IN3CS 7FBB IN3BC 7FBC IN4CS 7FBD IN4BC 7FBE IN5CS 7FBF IN5BC 7FC0 IN6CS 7FC1 IN6BC 7FC2 IN7CS 7FC3 IN7BC 7FC4 (reserved) 7FC5 OUT0BC 7FC6 OUT1CS 7FC7 OUT1BC 7FC8 OUT2CS 7FC9 OUT2BC 7FCA OUT3CS 7FCB OUT3BC 7FCC OUT4CS 7FCD OUT4BC 7FCE OUT5CS 7FCF OUT5BC
0 IN7IR OUT7IR 0 IN7IEN 0 * EP7IR EP7IE A15 A7 * * * * * * * * * * * * * * * * * * * * * * * * * * *
IV4 IN6IR OUT6IR 0 IN6IEN 0 * EP6IR EP6IE A14 A6 * d6 * d6 * d6 * d6 * d6 * d6 * d6 * d6 d6 * d6 * d6 * d6 * d6 * d6
IV3 IN5IR OUT5IR IBNIR IN5IEN IBNIE * EP5IR EP5IE A13 A5 * d5 * d5 * d5 * d5 * d5 * d5 * d5 * d5 d5 * d5 * d5 * d5 * d5 * d5
IV2 IN4IR OUT4IR URESIR IN4IEN URESIE INT2SFC EP4IR EP4IE A12 A4 * d4 * d4 * d4 * d4 * d4 * d4 * d4 * d4 d4 * d4 * d4 * d4 * d4 * d4
IV1 IN3IR OUT3IR SUSPIR IN3IEN
IV0 IN2IR OUT2IR SUTOKIR IN2IEN
0 IN1IR OUT1IR SOFIR IN1IEN SOFIE BPEN EP1IR EP1IE A9 A1 HSNAK d1 in1bsy d1 in2bsy d1 in3bsy d1 in4bsy d1 in5bsy d1 in6bsy d1 in7bsy d1 d1 out1bsy d1 out2bsy d1 out3bsy d1 out4bsy d1 out5bsy d1
0 IN0IR OUT0IR SUDAVIR IN0IEN SUDAVIE AVEN EP0IR EP0IE A8 A0 EP0STAL L d0 in1stl d0 in2stl d0 in3stl d0 in4stl d0 in5stl d0 in6stl d0 in7stl d0 d0 out1stl d0 out2stl d0 out3stl d0 out4stl d0 out5stl d0
OUT7IEN OUT6IEN OUT5IEN OUT4IEN OUT3IEN OUT2IEN OUT1IEN OUT0IEN SUSPIE SUTOKIE BREAK EP3IR EP3IE A11 A3 OUTBSY d3 * d3 * d3 * d3 * d3 * d3 * d3 * d3 d3 * d3 * d3 * d3 * d3 * d3 BPPULSE EP2IR EP2IE A10 A2 INBSY d2 * d2 * d2 * d2 * d2 * d2 * d2 * d2 d2 * d2 * d2 * d2 * d2 * d2
Bulk Endpoints 0-7
Document #: 38-08005 Rev. *B
Page 27 of 42
CY7C64613
4.0
Addr
Register Summary (continued)
Name Description D7 D6 D5 D4 D3 D2 D1 D0
7FD0 OUT6CS 7FD1 OUT6BC 7FD2 OUT7CS 7FD3 OUT7BC 7FD4 SUDPTRH 7FD5 SUDPTRL 7FD6 USBCS 7FD7 TOGCTL 7FD8 USBFRAMEL 7FD9 USBFRAMEH 7FDA (reserved) 7FDB FNADDR 7FDC (reserved) 7FDD USBPAIR 7FDE IN07VAL 7FDF OUT07VAL 7FE0 INISOVAL 7FE1 OUTISOVAL 7FE2 FASTXFR 7FE3 AUTOPTRH 7FE4 AUTOPTRL 7FE5 AUTODATA 7FE6-7FE7 (reserved)
Setup Data
Control & Status Byte Count Control & Status Byte Count Setup Data Ptr H Setup Data Ptr L USB Control & Status Toggle Control Frame Number L Frame Number H Function Address Endpoint Control Input Endpoint 0-7 valid Output Endpoint 0-7 valid Input EP 8-15 valid Output EP 8-15 valid Fast Transfer Mode Auto-Pointer H Auto-Pointer L Auto Pointer Data
* * * * A15 A7 WakeSRC Q FC7 0 0 ISOsend 0 IN7VAL
* d6 * d6 A14 A6 * S FC6 0 FA6 * IN6VAL
* d5 * d5 A13 A5 * R FC5 0 FA5
* d4 * d4 A12 A4 * IO FC4 0 FA4
* d3 * d3 A11 A3 DisCon 0 FC3 0 FA3
* d2 * d2 A10 A2 DiscOE EP2 FC2 FC10 FA2 PR6IN IN2VAL
out6bsy d1 out7bsy d1 A9 A1 ReNum EP1 FC1 FC9 FA1 PR4IN IN1VAL
out6stl d0 out7stl d0 A8 A0 SIGRSUME EP0 FC0 FC8 FA0 PR2IN 1 1 IN8VAL
Global USB Registers
PR6OUT PR4OUT PR2OUT IN5VAL IN4VAL IN3VAL
OUT7VA OUT6VA OUT5VA OUT4VA OUT3VA OUT2VA OUT1VA L L L L L L L IN15VAL IN14VAL IN13VAL IN12VAL OUT15V AL FISO A15 A7 D7 OUT14V OUT13V OUT12V AL AL AL FBLK A14 A6 D6 RPOL A13 A5 D5 RMOD1 A12 A4 D4 IN11VAL IN10VAL OUT11V AL RMOD0 A11 A3 D3 IN9VAL
OUT10V OUT9VA OUT8VA AL L L WPOL A10 A2 D2 WMOD1 A9 A1 D1 WMOD0 A8 A0 D0
7FE8 SETUPDAT 7FF0 OUT8ADDR 7FF1 OUT9ADDR 7FF2 OUT10ADDR 7FF3 OUT11ADDR 7FF4 OUT12ADDR 7FF5 OUT13ADDR 7FF6 OUT14ADDR 7FF7 OUT15ADDR 7FF8 IN8ADDR 7FF9 IN9ADDR 7FFA IN10ADDR 7FFB IN11ADDR 7FFC IN12ADDR 7FFD IN13ADDR 7FFE IN14ADDR 7FFF IN15ADDR
8 bytes of SETUP data Endpt 8 OUT Start Addr Endpt 9 OUT Start Addr Endpt 10 OUT Start Addr Endpt 11 OUT Start Addr Endpt 12 OUT Start Addr Endpt 13 OUT Start Addr Endpt 14 OUT Start Addr Endpt 15 OUT Start Addr Endpt 8 IN Start Addr Endpt 9 IN Start Addr Endpt 10 IN Start Addr Endpt 11 IN Start Addr Endpt 12 IN Start Addr Endpt 13 IN Start Addr Endpt 14 IN Start Addr Endpt 15 IN Start Addr
d7 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9
d6 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8
d5 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7
d4 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6
d3 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5
d2 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4
d1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Isochronous FIFO Sizes
Document #: 38-08005 Rev. *B
Page 28 of 42
CY7C64613
5.0 Input/Output Pin Special Consideration
The EZ-USB FX has a weak internal pull-up resistor that is present on the inputs and outputs when the external signal level is a high (above 1.3V). The weak internal pull-up is not present in the circuit when the voltage level of the external signal is low. Since the weak pull-up is only in the circuit when the external signal level is high, this means that if the last voltage level driven on the pin was a high, the pull-up resistor will keep it high. However, if the last voltage level driven on the pin was a low then the pull-up is turned off and the pad can float until it gets to a high logic level. This situation affects both inputs as well as outputs that are three-stated. Use a 25-K ohms or lower pull-down resistor to bring a pin to a low level if needed.
6.0
Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................-65C to +150C Ambient Temperature with Power Supplied ...............................................................................................................0C to +70C Supply Voltage on VCC relative to GND.................................................................................................................. -0.5V to +4.0V DC Input Voltage.................................................................................................................................................... -0.5V to 5.25V DC Voltage Applied to Outputs in High Z State...............................................................................................-0.5V to VCC + 0.5V Power Dissipation ..............................................................................................................................................................500 mW Static Discharge Voltage .......................................................................................................................................................> 2 kV Latch-up Current ............................................................................................................................................................. > 200 mA Max Output Sink Current ..................................................................................................................................................... 10 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ......................................................................................................................0C to +70C Supply Voltage ........................................................................................................................................................ +3.0V to +3.6V Ground Voltage .......................................................................................................................................................................... 0V FOSC (Oscillator or Crystal Frequency) ............................................................................................................. 12 MHz 0.20%[3]
8.0
DC Characteristics
Conditions Min. 3.0 2 -0.5 2.4 0.4 10 275[5] 50[4] 3.6 0.3 44 44 5 10 Typ. Max. 3.6 5.25 0.8 10 Unit V V V A V V pF A mA V V A A
Parameter Description VCC Supply Voltage VIH Input High Voltage VIL Input Low Voltage II Input Leakage Current VOH Output Voltage High VOL Output Low Voltage CIN Input Pin Capacitance Suspend Current ISUSP ICC Supply Current USB Transceiver VOH Output Voltage High VOL Output Low Voltage RpH Output Impedance (HIGH state) RpL Output Impedance (LOW state) Ii Input Leakage Current Ioz Three-State Output OFF-State Current
0< VIN < VCC IOUT = 1.6 mA IOUT = -1.6 mA
8051 running, connected to USB IOUT = 1.6 mA IOUT = -1.6 mA Includes external 22 5% resistor Includes external 22 5% resistor VCC = 3.6V; VI = 5.5V or GND; not for IO pins VI = VIH or VIL; VO = VCC or GND 2.8 0.0 28 28
120 35
0.1
Notes: 3. The USB Specification requires that the full-speed data rate when transmitting is 12.000 Mb/s 0.25% (2,500 ppm). Hence, the allowed variance of Fosc must be tighter than 0.25% to guarantee 0.25% when transmitting on the USB. 4. A guideline only. Not guaranteed. 5. Maximum suspend current is not guaranteed.
Document #: 38-08005 Rev. *B
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CY7C64613
9.0
9.1
AC Electrical Characteristics
USB Transceiver
Specified Conditions: per Table 7-9 Full-speed Source Electrical Characteristics Revision 2.0 of the USB specification Parameter Trise Tfall tRFM Vcr Rise/Fall Time Matching Crossover Point Description Rise and Fall Times Full Speed Condition Min. 4 4 90 1.3 Max. 20 20 110 2.0 Unit ns ns % V
9.2
Program Memory Read
t CL
CLKO UT
Note 6
tAV
tAV
A[15..0]
t STBL tSTBH
PSEN#
t AC C 1
[7]
t D SU da ta in
t DH
D[7..0]
f1_8051_pgm em rd.vsd
Parameter tCL tAV tSTBL tSTBH tDSU tDH
Description 1/CLKOUT Frequency Delay from Clock to Valid Address Clock to PSEN# Low Clock to PSEN# High Data Set-up to Clock Data Hold Time
Min.
Typ. 41.66 20.83
Max.
Unit ns ns
Notes 24 MHz 48 MHz
0 0 0 10 0
10 8 8
ns ns ns ns ns
Notes: 6. CLKOUT is shown with positive polarity. 7. tACC1 is computed from the above parameters as follows: tACC1(24 MHz) = 3*tCL - tAV -tDSU = 106 ns tACC1(48 Mhz) = 3*tCL - tAV - tDSU = 44 ns.
Document #: 38-08005 Rev. *B
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CY7C64613
9.3 Data Memory Read
tCL
Stretch=0
CLKOUT
tAV tSTBL tSTBH tAV
A[15..0] RD#
tACC2 [8] tDSU
data in
tDH
D[7..0]
tCL
Stretch=1
CLKOUT
tAV
A[15..0] RD#
tACC3
[8]
tDSU
data in
tDH
D[7..0]
f2_8051_datamemrd.vsd
Parameter tCL tAV tSTBL tSTBH tDSU tDH
Description 1/CLKOUT Frequency Delay from Clock to Valid Address Clock to RD Low Clock to RD High Data Set-up to Clock Data Hold Time
Min.
Typ. 41.66 20.83
Max.
Unit ns ns
Notes 24 MHz 48 MHz
0 0 0 0
10 8 8 10
ns ns ns ns ns
Note: 8. tACC2 and tACC3 are computed from the above parameters as follows: tACC2(24 MHz) = 3*tCL - tAV -tDSU = 106 ns tACC2(48 Mhz) = 3*tCL - tAV - tDSU = 44 ns tACC3(24 MHz) = 5*tCL - tAV -tDSU = 188 ns tACC3(48 Mhz) = 5*tCL - tAV - tDSU = 85 ns.
Document #: 38-08005 Rev. *B
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CY7C64613
9.4 Data Memory Write
S tretch = 0
t CL
C LK OUT
t AV t STBL t STBH t AV
A [15..8]
W R#
tO N 1 tOF F 1 data out
D [7..0]
S tretch = 1
tCL
C LK OUT
t AV tAV
A [15..8]
W R#
tO N 1 tO F F 1 data out
D [7..0]
Parameter tAV tSTBL tSTBH tON1 tOFF1
Description Delay from Clock to Valid Address Clock to WR Pulse Low Clock to WR Pulse High Clock to Data Turn-on Clock to Data Hold Time
Min. 0 0 0 0 -2
Max. 10 8 8 7 7
Unit ns ns ns ns ns
Notes
Document #: 38-08005 Rev. *B
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CY7C64613
9.5 DMA Read
tCL
non-burst
CLKOUT
tAV
A[15..0]
Note 9
RD#/FRD# CS#, OE#
Note 10
tSTBL
tSTBH
tDSU
in
tDH
in in
D[7..0]
tCL
burst
CLKOUT
tAV
A[15..0]
Note 9
RD#/FRD# CS#, OE# D[7..0]
tSTBL
tSTBH
tDSU
in
tDH
in in in in
f4_dmard.vsd
Parameter tAV tSTBL tSTBH tDSU tDH
Description Delay from Clock to Valid Address Clock to Strobe Low Clock to Strobe High Data to Clock Set-up Clock to Data Hold
Min. 0 0 0 10 0
Max. 10 8 8
Unit ns ns ns ns ns
Notes Non-burst Non-burst
Notes: 9. The address bus is not used in external FIFO transfers that use FRD#. 10. This is the maximum data rate. The strobes are programmable for longer access times.
Document #: 38-08005 Rev. *B
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CY7C64613
9.6 DMA Write
t CL
Non - Burst
CLK OUT
t AV
A [15..0] Note 11
tSTBL tSTBH
W R#/FW R# CS #, OE # Note 12 D[7..0]
t ON 1
tD A
t OFF1
t CL
Burst
CLK OUT
tAV
A [15..0] Note 11
tSTBL tSTBH
W R#/FW R# CS #, OE #
tD A
D[7..0]
f5_dm awr.v s d
Parameter tAV tSTBL tSTBH tDA tON1 tOFF1
Description Clock to Address Valid Clock to Strobe Low Clock to Strobe High Clock to Valid Data Clock to Data Turn-on Clock to Data Hold Time
Min. 0 0 0 0 -2
Max. 10 8 8 12 7 7
Unit ns ns ns ns ns ns
Notes Non-burst Non-burst
Notes: 11. The address bus in not used in external FIFO transfers (FWR# strobe). 12. This is the maximum data rate. The WR/FWR pulses are programmable for longer access times.
Document #: 38-08005 Rev. *B
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CY7C64613
9.7 Slave FIFOs--Output Enables
AOE BOE AFI [7..0] BFI [7..0]
tON tOFF
f6_fifo_sync_oe.vsd
Parameter tON tOFF
Description FIFO Data Bus Turn-on Time FIFO Data Bus Turn-off Time
Min. 0 0
Max. 10 10
Unit ns ns
9.8
Slave FIFOs--Synchronous Read
tCL
XCLK
[13]
tSUX
t XH
ASEL/BSEL SLRD
t XDA
AFI/BFI [7..0]
tXF LAG
FLAGS
f7_fifo_sync_read.vsd
Parameter tSUX tXH tXDA tXFLAG
Description Strobe and Sel to External Clock Set-up Time External Clock to Strobe and Sel Hold Time Clock to A/B FIFO data Clock to FIFO flag
Min. 6
Max. 9 13 2tCL+11
Unit ns ns ns ns
Note: 13. XCLK must be greater than or equal to 5 MHz, and less than (but not equal to) 48 MHz and must be free running.
Document #: 38-08005 Rev. *B
Page 35 of 42
CY7C64613
9.9 Slave FIFOs--Synchronous Write
tCL
XCLK [13]
t SU X tXH
ASEL/BSEL SLWR AFI/BFI [7..0] FLAGS
f8_fifo_sync_write.vsd
valid
tXFLAG
Parameter tCL tSUX tXH tXFLAG CLKOUT Period
Description
Min.
Typ. 41.66 20.83
Max.
Unit ns ns ns ns
Sel, Strobe & Data Set-up to External Clock External Clock to Sel, Strobe & Data Hold Time External Clock to FIFO Flag
9 2 2tCL+11
ns
9.10
Slave FIFOs--Asynchronous Read[14, 15]
Note 16
A S E L/B S E L
t RDL t RDH
S LRD
t
AC C A
A FI/B FI [7..0]
t
AFLAG
FLA GS
f9_fifo_as y nc _read.v s d
Parameter tRDL tRDH tACCA tAFLAG
Description SLRD strobe active SLRD strobe inactive Read active to FIFO data valid SLRD inactive to FIFO flag
Min. 30 70 90
Max.
Unit ns ns ns
Notes
double byte mode
40 95
ns ns
Notes: 14. The timing diagram assumes OEA/OEB is active. 15. The read operation begins when both A/BSEL and SLRD are active, and ends when either is inactive. 16. The polarities of ASEL/BSEL and SLRD are programmable. Active-LOW is shown.
Document #: 38-08005 Rev. *B
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CY7C64613
9.11 Slave FIFOs--Asynchronous Write[14, 15]
Note 16
ASEL/BSEL
t
W RL
t
W RH
SLW R
t
S UA
t
HA
AFI/BFI [7..0]
t
AFLAG
FLAGS
f10_fi fo_as y nc _wri te.v s d
Parameter tWRL tWRH tSUA tHA tAFLAG
Description Slave Write Strobe Active Slave Write Strobe Inactive Async Data Set-up Time to Write Strobe Inactive Async Data Hold Time to Write Strobe Inactive Async Write Strobe Inactive to FIFO Flag Valid
Min. 30 70 10 5
Max.
Unit ns ns ns ns
95
ns
9.12
GPIF - Clocked with Fixed 48-MHz Internal Clock
tCL
Internal (48MHz )
t SRY tRY H
R D Yn
G D [15..0] (input) C T Ln and GD [15..0] (output)
Parameter tSRY tRYH tXGD tCL
va lid
t XG D
Description Set-up time: RDYn and GPIF Data to External Clock Hold time: External Clock to RDYn and GPIF Data Clock to GPIF Data and CTLn output Clock Period
Min. 2
Max. 9 13
Unit ns ns ns ns
20.83
20.83
Document #: 38-08005 Rev. *B
Page 37 of 42
CY7C64613
9.13 GPIF Signals Externally Clocked - XCLK
tCL
XC LK (input)
tSR X t RY X
R D Yn
GD [15..0] (input) C TLn and GD [15..0] (output)
Parameter tSRX tRYX tXGX tCL
va lid
t XG X
Description Set-up Time: RDYn and GPIF Data to External Clock Hold Time: External Clock to RDYn and GPIF Data Clock to GPIF Data and CTLn output XCLK Period
Min. 9 2
Max.
Unit ns ns
13 21[17] 200[17]
ns ns
10.0
Ordering Information
Part Number Package Type 52 PQFP 80 PQFP 128 PQFP CY3671 RAM Size 8K 8K 8K Burst I/O Rate (Bytes/sec) 48 Mbytes 96 Mbytes 96 Mbytes # Prog I/Os 16 32 40 Dataport 8-bit 16-bit 16-bit + Addr Isochronous Support Yes Yes Yes
CY7C64613-52NC CY7C64613-80NC CY7C64613-128NC EZ-USB FX Xcelerator Development Kit
11.0
Package Diagrams
Key for all package diagrams: BSC = Basic Standard Configuration All dimensions are in millimeters (mm).
Note: 17. XCLK must be greater than or equal to 5 MHz, and less than (but not equal to) 48 MHz and must be free running.
Document #: 38-08005 Rev. *B
Page 38 of 42
CY7C64613
11.1 52 PQFP
52-Lead Plastic Quad Flatpack N52
51-85042-**
Document #: 38-08005 Rev. *B
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CY7C64613
11.2 80 PQFP
80-Lead Plastic Quad Flatpack (14 x 14 x 2.80 mm) N80A
51-85174-**
Document #: 38-08005 Rev. *B
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CY7C64613
11.3 128 PQFP
128-Lead Plastic Quad Flatpack
51-85080-*A
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C standard specification defined by Philips. EZ-USB is a registered trademark, and EZ-USB FX is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08005 Rev. *B
Page 41 of 42
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C64613
Document History Page
Document Title: CY7C64613 EZ-USB FXTM USB Microcontroller Document Number: 38-08005 REV. ** *A *B ECN NO. 110206 114944 125185 Issue Date 11/11/01 01/08/03 04/23/03 Orig. of Change SZV KKU KKU Description of Change Change from Spec number: 38-00903 to 38-08005 Corrected pinouts and register names in all sections. Removed CY7C64601 and CY7C64603 part number and references. Correct Figure 1-1, Centered 52 pin package in 11.1, Correct 128 pin package in 11.3
Document #: 38-08005 Rev. *B
Page 42 of 42

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